Epoch in Verilog

A common requirement in digital designs is generating or using timestamps. In Verilog, we don’t have built-in functions for Unix epoch time, but we can simulate similar behavior using system tasks and functions.

module epoch_example;
  
  // Define a 64-bit register to store our "timestamp"
  reg [63:0] current_time;
  
  initial begin
    // Use $time to get the current simulation time
    current_time = $time;
    $display("Current simulation time: %0d", current_time);
    
    // Simulate seconds since "epoch"
    $display("Seconds: %0d", current_time / 1000000000);
    
    // Simulate milliseconds since "epoch"
    $display("Milliseconds: %0d", current_time / 1000000);
    
    // Display nanoseconds (simulation time is typically in nanoseconds)
    $display("Nanoseconds: %0d", current_time);
    
    // Simulate converting back to a "time" representation
    #1000000000; // Wait for 1 second of simulation time
    $display("After 1 second: %0d", $time);
    
    #1234567; // Wait for 1,234,567 nanoseconds
    $display("After 1,234,567 nanoseconds: %0d", $time);
  end
  
endmodule

In this Verilog example:

1. We use a 64-bit register current_time to store our simulated timestamp.

2. The $time system function is used to get the current simulation time, which is typically in nanoseconds.

3. We perform some arithmetic to convert the nanosecond time to seconds and milliseconds.

4. We use delay statements (#) to simulate the passage of time in the simulation.

5. The $display system task is used to print values, similar to fmt.Println in the original example.

To run this Verilog simulation, you would typically use a Verilog simulator like ModelSim, VCS, or Icarus Verilog. The exact command would depend on your simulator, but it might look something like this:

$ iverilog -o epoch_sim epoch_example.v
$ ./epoch_sim
Current simulation time: 0
Seconds: 0
Milliseconds: 0
Nanoseconds: 0
After 1 second: 1000000000
After 1,234,567 nanoseconds: 1001234567

Note that in Verilog simulations, time starts from 0 at the beginning of the simulation, unlike real-world Unix epoch time. The concept of “epoch” in this context is more about tracking elapsed simulation time rather than a specific calendar date.

Next, we’ll look at other time-related tasks in Verilog simulations.