For in Verilog

Verilog uses always blocks for repetitive execution, which is similar to loops in other languages. Here are some basic types of always blocks and repetitive constructs in Verilog.

module for_example;
  integer i, j, n;

  initial begin
    // The most basic type, with a single condition.
    i = 1;
    while (i <= 3) begin
      $display(i);
      i = i + 1;
    end

    // A classic initial/condition/after loop.
    for (j = 0; j < 3; j = j + 1) begin
      $display(j);
    end

    // Verilog doesn't have a direct equivalent to Go's range,
    // but we can simulate it with a for loop.
    for (i = 0; i < 3; i = i + 1) begin
      $display("range", i);
    end

    // An infinite loop, which will run until a disable statement 
    // or the simulation ends.
    fork
      forever begin
        $display("loop");
        disable forever_loop;
      end
    join : forever_loop

    // Demonstrating continue behavior
    for (n = 0; n < 6; n = n + 1) begin
      if (n % 2 == 0) begin
        continue;
      end
      $display(n);
    end
  end
endmodule

To run this Verilog code, you would typically use a Verilog simulator. The output would look something like this:

1
2
3
0
1
2
range 0
range 1
range 2
loop
1
3
5

In Verilog, we use always blocks for continuous execution and initial blocks for sequential execution that happens once at the start of simulation. The forever loop is used for infinite loops, which can be controlled using disable statements.

Verilog doesn’t have built-in constructs exactly equivalent to Go’s range, but we can achieve similar functionality using standard for loops.

The continue statement in Verilog works similarly to Go, skipping the rest of the current iteration and moving to the next one.

We’ll see other forms of repetitive structures when we look at always blocks, event controls, and other Verilog-specific constructs.