Line Filters in Verilog

A line filter is a common type of program that reads input, processes it, and then outputs some derived result. In hardware design with Verilog, we can implement a similar concept using a module that processes input data and produces output data.

Here’s an example of a Verilog module that implements a simple line filter. It takes in 8-bit ASCII characters as input and outputs the uppercase version of those characters.

module line_filter(
    input wire clk,
    input wire reset,
    input wire [7:0] char_in,
    input wire char_valid,
    output reg [7:0] char_out,
    output reg char_ready
);

    // Internal registers
    reg [7:0] current_char;
    reg processing;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            char_out <= 8'b0;
            char_ready <= 1'b0;
            current_char <= 8'b0;
            processing <= 1'b0;
        end else begin
            if (char_valid && !processing) begin
                current_char <= char_in;
                processing <= 1'b1;
            end

            if (processing) begin
                // Convert lowercase to uppercase
                if (current_char >= 8'h61 && current_char <= 8'h7A) begin
                    char_out <= current_char - 8'h20;
                end else begin
                    char_out <= current_char;
                end
                char_ready <= 1'b1;
                processing <= 1'b0;
            end else begin
                char_ready <= 1'b0;
            end
        end
    end

endmodule

This Verilog module does the following:

It takes input characters through the char_in port when char_valid is high.
It processes each character, converting lowercase letters to uppercase.
It outputs the processed character through char_out and sets char_ready high to indicate valid output.

To use this module in a larger design, you would instantiate it and connect it to your input and output streams. Here’s a simple testbench to demonstrate its usage:

module testbench;
    reg clk, reset;
    reg [7:0] char_in;
    reg char_valid;
    wire [7:0] char_out;
    wire char_ready;

    // Instantiate the line_filter module
    line_filter uut (
        .clk(clk),
        .reset(reset),
        .char_in(char_in),
        .char_valid(char_valid),
        .char_out(char_out),
        .char_ready(char_ready)
    );

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        clk = 0;
        reset = 1;
        char_in = 0;
        char_valid = 0;

        #10 reset = 0;

        // Test lowercase 'a'
        #10 char_in = 8'h61; char_valid = 1;
        #10 char_valid = 0;
        #10;

        // Test uppercase 'B'
        #10 char_in = 8'h42; char_valid = 1;
        #10 char_valid = 0;
        #10;

        // Test number '3'
        #10 char_in = 8'h33; char_valid = 1;
        #10 char_valid = 0;
        #10;

        $finish;
    end

    // Monitor the output
    always @(posedge clk) begin
        if (char_ready)
            $display("Output: %c", char_out);
    end

endmodule

To simulate this design, you would use a Verilog simulator such as ModelSim, VCS, or Icarus Verilog. The simulation would show the module converting lowercase letters to uppercase while leaving other characters unchanged.

This Verilog implementation provides a hardware-based approach to line filtering, which could be used in FPGA designs or ASICs for real-time text processing applications.

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Line Filters in Verilog