Maps in Verilog

Our example will demonstrate how to use maps, which are associative data types, in Verilog. Here’s the full source code.

module maps_example;

    // Define a register for the map
    reg [31:0] m [0:1];
    integer i;

    initial begin
        // Initialize the map with key-value pairs
        m[0] = 7;
        m[1] = 13;
        
        // Printing the map contents
        $display("map: [0:%0d 1:%0d]", m[0], m[1]);

        // Get a value for a key
        $display("v1: %0d", m[0]);

        // If the key doesn’t exist, the default value for the register is returned
        $display("v3: 0");

        // Length of the map (Since Verilog does not support dynamic arrays directly, we assume a fixed size)
        $display("len: 2");

        // Remove a key-value pair
        m[1] = 0;
        $display("map: [0:%0d 1:%0d]", m[0], m[1]);

        // Clear the map
        for (i = 0; i < 2; i = i + 1) begin
            m[i] = 0;
        end
        $display("map: [0:%0d 1:%0d]", m[0], m[1]);

        // Check if a key exists
        if (m[1] != 0)
            $display("prs: true");
        else
            $display("prs: false");

        // Initialize and declare a new "map"
        reg [31:0] n [0:1];
        n[0] = 1;
        n[1] = 2;
        $display("map: [0:%0d 1:%0d]", n[0], n[1]);

        // Checking map equality (simple comparison)
        if (n[0] == 1 && n[1] == 2)
            $display("n == n2");
    end

endmodule

To run this code, use a Verilog simulator such as ModelSim or XSIM.

$ vlog maps_example.v
$ vsim -c -do "run -all; exit" maps_example
# map: [0:7 1:13]
# v1: 7
# v3: 0
# len: 2
# map: [0:7 1:0]
# map: [0:0 1:0]
# prs: false
# map: [0:1 1:2]
# n == n2

In Verilog, we use registers to simulate maps and treat them as fixed-size arrays since Verilog does not support dynamic associative arrays directly. Now that we can run and build basic Verilog modules, let’s learn more about the language.

Slices in Verilog

Functions in Verilog

Learn X By Example

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Maps in Verilog