String Functions in Verilog

Verilog doesn’t have built-in string manipulation functions like other high-level programming languages. However, we can demonstrate similar concepts using SystemVerilog, which is an extension of Verilog and provides more advanced features, including string manipulation.

module string_functions;
  
  // We'll use a function to print our results
  function automatic void print(string message);
    $display(message);
  endfunction

  initial begin
    string test_string = "test";
    string[] array = '{"a", "b"};

    // Contains
    print($sformatf("Contains:  %0d", test_string.len() > 0 && test_string.substr(1, 2) == "es"));

    // Count
    print($sformatf("Count:     %0d", test_string.len() - test_string.substitute("t", "")));

    // HasPrefix
    print($sformatf("HasPrefix: %0d", test_string.substr(0, 2) == "te"));

    // HasSuffix
    print($sformatf("HasSuffix: %0d", test_string.substr(test_string.len()-2, 2) == "st"));

    // Index
    print($sformatf("Index:     %0d", test_string.indexOf("e")));

    // Join
    print($sformatf("Join:      %s", {array[0], "-", array[1]}));

    // Repeat
    print($sformatf("Repeat:    %s", {5{"a"}}));

    // Replace
    print($sformatf("Replace:   %s", test_string.substitute("o", "0")));

    // Split
    string split_string = "a-b-c-d-e";
    string split_result[$];
    int last_index = 0;
    for (int i = 0; i < split_string.len(); i++) begin
      if (split_string[i] == "-") begin
        split_result.push_back(split_string.substr(last_index, i-last_index));
        last_index = i + 1;
      end
    end
    split_result.push_back(split_string.substr(last_index, split_string.len()-last_index));
    print($sformatf("Split:     %p", split_result));

    // ToLower and ToUpper
    print($sformatf("ToLower:   %s", test_string.tolower()));
    print($sformatf("ToUpper:   %s", test_string.toupper()));
  end

endmodule

This SystemVerilog code demonstrates similar functionality to the original example, using SystemVerilog’s string manipulation methods where available. Here are some key points:

SystemVerilog provides built-in methods for strings, such as len(), substr(), indexOf(), tolower(), and toupper().
Some functions like Contains, Count, HasPrefix, and HasSuffix are implemented using a combination of these built-in methods.
The Join operation is simulated using string concatenation.
Replace is implemented using the substitute() method.
Split is implemented manually using a loop and the substr() method, as SystemVerilog doesn’t have a built-in split function.
SystemVerilog uses $display for printing, which is wrapped in a function named print for consistency with the original example.

To run this code, you would need a SystemVerilog simulator. The output would be similar to the original example, demonstrating various string operations in SystemVerilog.

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