Command Line Arguments in VHDL

Command-line arguments are a common way to parameterize execution of programs. For example, ghdl -r hello uses -r and hello arguments to the ghdl program.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity CommandLineArguments is
end CommandLineArguments;

architecture Behavioral of CommandLineArguments is
begin
    process
        variable argsWithProg : string(1 to 100);
        variable argsWithoutProg : string(1 to 100);
        variable arg : string(1 to 20);
    begin
        -- In VHDL, we don't have direct access to command-line arguments
        -- This is typically handled by the simulation environment
        -- For demonstration, we'll use hardcoded values
        
        argsWithProg := "./command-line-arguments a b c d";
        argsWithoutProg := "a b c d                    ";
        arg := "c                 ";
        
        report "argsWithProg: " & argsWithProg;
        report "argsWithoutProg: " & argsWithoutProg;
        report "arg: " & arg;
        
        wait;
    end process;
end Behavioral;

In VHDL, we don’t have direct access to command-line arguments within the language itself. This functionality is typically provided by the simulation or synthesis tool being used. The above code demonstrates the concept using hardcoded values.

To simulate this VHDL code, you would typically use a tool like GHDL:

$ ghdl -a command_line_arguments.vhd
$ ghdl -e CommandLineArguments
$ ghdl -r CommandLineArguments
argsWithProg: ./command-line-arguments a b c d
argsWithoutProg: a b c d
arg: c

Note that the actual output and method of passing command-line arguments would depend on your specific VHDL simulation environment. Some simulators provide mechanisms to pass arguments to the VHDL code, but this is not part of the VHDL language standard.

In real-world VHDL designs, parameters are typically set using generics or configuration specifications rather than command-line arguments. These provide a more standardized way of parameterizing VHDL designs across different tools and environments.

Next, we’ll look at more advanced ways of parameterizing VHDL designs using generics and configurations.