Command Line Flags in VHDL

Our first program will demonstrate how to handle command-line flags in VHDL. Here’s the full source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity CommandLineFlags is
    generic (
        WORD : string := "foo";
        NUMB : integer := 42;
        FORK : boolean := false;
        SVAR : string := "bar"
    );
end CommandLineFlags;

architecture Behavioral of CommandLineFlags is
begin
    process
    begin
        report "word: " & WORD;
        report "numb: " & integer'image(NUMB);
        report "fork: " & boolean'image(FORK);
        report "svar: " & SVAR;
        wait;
    end process;
end Behavioral;

In VHDL, we don’t have a direct equivalent to command-line flags as in software programming languages. Instead, we use generics to pass configurable parameters to our design. These generics can be thought of as similar to command-line flags in the context of hardware description.

We declare our entity CommandLineFlags with four generics:

• WORD: a string with default value “foo”
• NUMB: an integer with default value 42
• FORK: a boolean with default value false
• SVAR: a string with default value “bar”

In the architecture, we use a process to report the values of these generics, which is analogous to printing the values of command-line flags.

To “run” this VHDL code, you would typically simulate it using a VHDL simulator. The simulation might look like this:

# Default values
word: foo
numb: 42
fork: false
svar: bar

To change the “flag” values, you would modify the generic map when instantiating this entity in a testbench or higher-level design. For example:

UUT: entity work.CommandLineFlags
    generic map (
        WORD => "opt",
        NUMB => 7,
        FORK => true,
        SVAR => "flag"
    );

This would produce output similar to:

word: opt
numb: 7
fork: true
svar: flag

Note that in VHDL, we don’t have the concept of “positional arguments” or dynamic flag parsing as in software. All parameters (generics) must be explicitly defined in the entity declaration, and their values are typically set at elaboration time, before simulation begins.

Also, VHDL doesn’t have built-in help text generation for generics. Documentation for generics is typically provided in comments or separate documentation files.

This VHDL implementation provides a way to configure parameters of a design, which is conceptually similar to using command-line flags in software, albeit with the limitations and differences inherent to hardware description languages.