Learn X By Example
Learn X By Example

    Constants in VHDL

    Constants in VHDL are similar to those in many other programming languages. VHDL supports various types of constant values such as character, string, boolean, and numeric values.

    In this example, we’ll see how constants are declared and used in VHDL.

    Declaration of Constants in VHDL

    library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;

entity ConstantExample is
end ConstantExample;

architecture Behavioral of ConstantExample is

    -- Declare a string constant
    constant s : string := "constant";

    -- Declare a numeric constant
    constant n : integer := 500000000;

    -- Declare a constant for a real number expression
    constant d : real := 3e20 / n;

begin

    process
    begin
        -- Print the string constant
        report s;

        -- Print the real constant
        report real'image(d);

        -- Explicit type conversion to integer
        report integer'image(integer(d));

        -- Using the constant in a mathematical function
        report real'image(sin(real(n)));

        wait;
    end process;

end Behavioral;

    Explanation

    To declare a constant in VHDL, you use the constant keyword.

    constant s : string := "constant";

    This declares a string constant s with the value "constant".

    constant n : integer := 500000000;

    This declares an integer constant n with the value 500000000.

    constant d : real := 3e20 / n;

    This declares a real constant d with the value of 3e20 divided by n. In constants, arithmetic expressions are computed with arbitrary precision.

    In the process, we print out the constants with the report statement:

    report s;              -- Print string constant
report real'image(d);  -- Print real constant
report integer'image(integer(d)); -- Explicit type conversion to integer
report real'image(sin(real(n))); -- Using the constant in a mathematical function

    The report statement outputs the values and the real'image and integer'image functions are used for converting numerical values to string representations.

    This VHDL example shows how to declare and use constants, perform arithmetic with constants, and print out their values using the report statement.

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