Goroutines in VHDL

A process in VHDL is a concurrent statement that includes sequential statements. Below is an example demonstrating a simple process.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ProcessExample is
end ProcessExample;

architecture Behavioral of ProcessExample is
begin

    process
        variable i : integer := 0;
    begin
        for i in 0 to 2 loop
            report "direct : " & integer'image(i);
        end loop;
        
        -- To simulate concurrency, we can use another process
        process
            variable j : integer := 0;
        begin
            for j in 0 to 2 loop
                report "process : " & integer'image(j);
            end loop;
            wait;
        end process;
        
        -- Another process to simulate an anonymous process
        process
        begin
            report "going";
            wait;
        end process;
        
        wait;
    end process;

end Behavioral;

To run the simulation, use your preferred VHDL simulation software. The expected output will show the sequential execution, mimicking concurrency by executing the processes in sequence during the simulation time.

When the simulation runs, you will see the output from the first process followed by the outputs of the subsequent processes. The order of the output may vary depending on how the simulator schedules the processes.

Next, let’s explore another aspect of concurrency in VHDL: signals and how processes can communicate using signals.

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Goroutines in VHDL