Hello World in VHDL

Our first program will print the classic “hello world” message. Here’s the full source code.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity HelloWorld is
end HelloWorld;

architecture Behavior of HelloWorld is
begin
    process
    begin
        report "hello world";
        wait;
    end process;
end Behavior;

To run the program, you would typically simulate it using a VHDL simulation tool. VHDL code is used primarily for describing hardware, so it doesn’t run like a typical software program but rather is tested through simulation or synthesized into hardware.

To simulate the code, you might use a tool like GHDL or ModelSim:

# Analyze the VHDL file
$ ghdl -a HelloWorld.vhdl

# Elaborate the design
$ ghdl -e HelloWorld

# Run the simulation
$ ghdl -r HelloWorld
hello world

Sometimes we’ll want to synthesize our VHDL code into an actual hardware design and deploy it to FPGA or ASIC. This process involves using specific synthesis tools provided by hardware vendors (e.g., Xilinx Vivado, Intel Quartus).

Now that we can simulate and build basic VHDL designs, let’s learn more about the language.