Range Over Channels in VHDL

In a previous example, we saw how for loops provide iteration over basic data structures. In VHDL, we can use similar constructs to iterate over values in an array or signals.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RangeOverArray is
end RangeOverArray;

architecture Behavioral of RangeOverArray is
    type string_array is array (0 to 1) of string(1 to 3);
    signal queue : string_array := ("one", "two");
    
begin
    process
    begin
        -- We'll iterate over 2 values in the queue array.
        for i in queue'range loop
            report queue(i);
        end loop;
        
        wait;
    end process;
end Behavioral;

This example demonstrates how to iterate over elements in an array. Since VHDL doesn’t have built-in channels like some other languages, we’re using an array to represent our queue of strings.

The for loop iterates over each element in the queue array. We use the queue'range attribute to specify the range of the loop, which will cover all elements in the array.

When you simulate this VHDL code, you should see output similar to:

# one
# two

This example shows how to iterate over a fixed array in VHDL. While VHDL doesn’t have the concept of channels or dynamic queues like some other languages, you can use arrays and other data structures to achieve similar functionality in your designs.

It’s worth noting that in hardware description languages like VHDL, the concept of “closing” a channel or array doesn’t directly apply. The array size and contents are typically static and determined at synthesis time. For dynamic behavior, you would need to implement more complex logic using processes and signals.