Struct Embedding in VHDL

VHDL supports the concept of component instantiation, which is similar to struct embedding in other languages. This allows for a more seamless composition of types.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity base is
    Port ( num : in integer );
end base;

architecture Behavioral of base is
begin
    -- This process simulates the 'describe' method
    process(num)
    begin
        report "base with num=" & integer'image(num);
    end process;
end Behavioral;

entity container is
    Port ( num : in integer;
           str : in string );
end container;

architecture Behavioral of container is
    -- This is similar to embedding in other languages
    component base
        Port ( num : in integer );
    end component;
begin
    -- Instantiate the base component
    base_inst: base port map (num => num);

    -- This process demonstrates accessing the 'embedded' component
    process(num, str)
    begin
        report "container: num=" & integer'image(num) & ", str=" & str;
    end process;
end Behavioral;

-- Test bench
entity tb_container is
end tb_container;

architecture Behavioral of tb_container is
    signal num : integer := 1;
    signal str : string(1 to 9) := "some name";
begin
    -- Instantiate the container
    uut: entity work.container
        port map (num => num, str => str);

    -- Stimulus process
    stim_proc: process
    begin
        wait for 10 ns;
        
        -- We can access the base's fields directly
        report "num: " & integer'image(num);
        report "str: " & str;
        
        wait;
    end process;
end Behavioral;

In this VHDL example, we’ve created a base entity with a num input and a process that reports its value, similar to the describe method in the original example. The container entity then instantiates the base entity as a component, which is analogous to embedding in other languages.

The test bench (tb_container) demonstrates how to use the container entity and access its fields. Note that VHDL doesn’t have the concept of methods in the same way as object-oriented languages, so we’ve used processes to simulate similar behavior.

To run this VHDL code, you would typically use a VHDL simulator such as ModelSim or GHDL. The simulation would output something like:

# Running simulation...
# base with num=1
# container: num=1, str=some name
# num: 1
# str: some name

This example demonstrates how VHDL can achieve a form of composition similar to struct embedding, albeit with different syntax and concepts specific to hardware description languages.

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Struct Embedding in VHDL