Tickers in VHDL

This example demonstrates how to create a periodic process in VHDL, similar to the concept of tickers in other languages. We’ll use a process with a wait statement to create a repeating event at regular intervals.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Ticker is
end Ticker;

architecture Behavioral of Ticker is
    signal done : boolean := false;
begin
    -- This process simulates a ticker that "ticks" every 500 ms
    ticker_process: process
    begin
        while not done loop
            wait for 500 ms;
            report "Tick at " & time'image(now);
        end loop;
        report "Ticker stopped";
        wait;
    end process;

    -- This process controls the duration of the simulation
    control_process: process
    begin
        wait for 1600 ms;
        done <= true;
        wait;
    end process;
end Behavioral;

In this VHDL code:

1. We define an entity called Ticker with no ports.

2. In the architecture, we declare a done signal to control when the ticker should stop.

3. The ticker_process simulates a ticker:

   • It runs in a loop until done becomes true.
   • Each iteration, it waits for 500 ms and then reports a “tick” message.
   • After the loop ends, it reports that the ticker has stopped.

4. The control_process simulates the main control flow:

   • It waits for 1600 ms (equivalent to the time.Sleep in the original code).
   • Then it sets done to true, which will stop the ticker process.

When you simulate this VHDL code, you should see output similar to this:

# Simulation output
Tick at 500 ms
Tick at 1000 ms
Tick at 1500 ms
Ticker stopped

The ticker “ticks” three times before it’s stopped, just like in the original example.

Note that VHDL is typically used for hardware description and simulation, so concepts like channels and goroutines don’t have direct equivalents. Instead, we use concurrent processes to simulate similar behavior. The wait statements in VHDL provide a way to create time-based events in simulation.