Timeouts in VHDL

Timeouts are important for systems that connect to external resources or that otherwise need to bound execution time. Implementing timeouts in VHDL can be achieved using wait statements with timeout clauses.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Timeouts is
end Timeouts;

architecture Behavioral of Timeouts is
    signal result1, result2 : std_logic_vector(7 downto 0);
    signal timeout1, timeout2 : std_logic;
begin
    -- For our example, suppose we're executing an external
    -- process that sets its result on signal 'result1'
    -- after 2 seconds.
    process
    begin
        wait for 2 sec;
        result1 <= x"01";  -- "result 1" in ASCII
    end process;

    -- Here's the process implementing a timeout.
    -- It waits for either the result or a timeout of 1 second.
    process
    begin
        wait for 1 sec;
        if result1 = x"00" then
            timeout1 <= '1';
        else
            timeout1 <= '0';
        end if;
    end process;

    -- If we allow a longer timeout of 3 seconds, then the result
    -- will be set before the timeout occurs.
    process
    begin
        wait for 2 sec;
        result2 <= x"02";  -- "result 2" in ASCII
    end process;

    process
    begin
        wait for 3 sec;
        if result2 = x"00" then
            timeout2 <= '1';
        else
            timeout2 <= '0';
        end if;
    end process;

    -- Process to display results
    process
    begin
        wait until timeout1 = '1' or result1 /= x"00";
        if timeout1 = '1' then
            report "timeout 1";
        else
            report "result 1";
        end if;

        wait until timeout2 = '1' or result2 /= x"00";
        if timeout2 = '1' then
            report "timeout 2";
        else
            report "result 2";
        end if;

        wait;
    end process;

end Behavioral;

Running this VHDL code in a simulation would show the first operation timing out and the second succeeding.

In VHDL, we don’t have the concept of channels or goroutines as in Go. Instead, we use concurrent processes and signals to model parallel behavior. The wait statement is used to introduce delays and implement timeouts.

Each process in this VHDL code runs concurrently, similar to goroutines in Go. The result1 and result2 signals are used to pass data between processes, analogous to channels in Go.

The timeout mechanism is implemented using wait statements with specific time delays. If the result signal is not set within the specified time, a timeout occurs.

To run this VHDL code, you would need to use a VHDL simulator, set up a testbench, and analyze the simulation results to see the timeout behavior.

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Timeouts in VHDL