Timers in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Timers is
end Timers;

architecture Behavioral of Timers is
    signal clk : std_logic := '0';
    signal timer1_done : std_logic := '0';
    signal timer2_done : std_logic := '0';
    signal timer2_stop : std_logic := '0';
begin
    -- Clock process (100 MHz)
    process
    begin
        wait for 5 ns;
        clk <= not clk;
    end process;

    -- Main process
    process(clk)
        variable counter1 : integer := 0;
        variable counter2 : integer := 0;
    begin
        if rising_edge(clk) then
            -- Timer 1: Wait for 2 seconds (200,000,000 clock cycles at 100 MHz)
            if counter1 < 200_000_000 then
                counter1 := counter1 + 1;
            else
                timer1_done <= '1';
            end if;

            -- Timer 2: Wait for 1 second (100,000,000 clock cycles at 100 MHz)
            if timer2_stop = '0' then
                if counter2 < 100_000_000 then
                    counter2 := counter2 + 1;
                else
                    timer2_done <= '1';
                end if;
            end if;
        end if;
    end process;

    -- Process to stop Timer 2
    process(clk)
    begin
        if rising_edge(clk) then
            if counter2 = 1000 then  -- Stop after 10 µs
                timer2_stop <= '1';
            end if;
        end if;
    end process;

    -- Simulation process
    process
    begin
        wait for 2 sec;
        assert timer1_done = '1' report "Timer 1 fired" severity note;
        assert timer2_stop = '1' report "Timer 2 stopped" severity note;
        wait;
    end process;
end Behavioral;

This VHDL code demonstrates the concept of timers, similar to the original example. Here’s how it works:

We define an entity Timers and its architecture Behavioral.
Inside the architecture, we create two timers using counters:
- Timer 1 waits for 2 seconds (equivalent to 200,000,000 clock cycles at 100 MHz).
- Timer 2 is set to wait for 1 second but can be stopped before it fires.
The main process increments the counters on each rising edge of the clock and sets the timer1_done and timer2_done signals when the respective timers fire.
A separate process is used to stop Timer 2 after a short period (10 µs in this example), demonstrating the ability to cancel a timer before it fires.
A simulation process waits for 2 seconds and then checks if Timer 1 has fired and Timer 2 has been stopped.

To run this VHDL code, you would typically use a VHDL simulator such as ModelSim or GHDL. The simulation will show that Timer 1 fires after 2 seconds, while Timer 2 is stopped before it has a chance to fire.

This example demonstrates how to implement timer-like behavior in VHDL using counters and clock cycles. While VHDL doesn’t have built-in timer functions like high-level programming languages, it provides low-level control that allows you to create precise timing mechanisms for hardware designs.

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