Values in VHDL

VHDL has various value types including strings, integers, floating-point numbers, booleans, etc. Here are a few basic examples.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Values is
end Values;

architecture Behavioral of Values is
begin
    process
    begin
        -- Strings, which can be concatenated with &
        report "vhdl" & "lang";
        
        -- Integers and floating-point numbers
        report "1+1 = " & integer'image(1 + 1);
        report "7.0/3.0 = " & real'image(7.0 / 3.0);
        
        -- Booleans, with boolean operators as you'd expect
        report boolean'image(true and false);
        report boolean'image(true or false);
        report boolean'image(not true);
        
        wait;
    end process;
end Behavioral;

To run this VHDL code, you would typically use a VHDL simulator. The output would look something like this:

# vsim -c work.values
# run -all
# vhdllang
# 1+1 = 2
# 7.0/3.0 = 2.333333e+00
# FALSE
# TRUE
# FALSE

In VHDL:

• Strings are concatenated using the & operator.
• Integer and floating-point arithmetic is supported directly.
• Boolean operations are similar to other languages.
• The report statement is used for output in simulation.
• Type conversion functions like integer'image and real'image are used to convert numbers to strings for reporting.

Note that VHDL is typically used for hardware description and simulation, so the concept of “running” the code is different from software languages. The code is usually simulated in a VHDL environment rather than compiled and executed like a traditional software program.