Variables in VHDL

Variables in VHDL are explicitly declared and used by the compiler to check type-correctness of signal assignments and function calls.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Variables is
end Variables;

architecture Behavioral of Variables is
begin
    process
        -- Variable declarations
        variable a : string(1 to 7) := "initial";
        variable b, c : integer := 1;
        variable d : boolean := true;
        variable e : integer;
        variable f : string(1 to 5) := "apple";
    begin
        -- Print variables
        report "a = " & a;
        
        c := 2;
        report "b = " & integer'image(b) & ", c = " & integer'image(c);
        
        report "d = " & boolean'image(d);
        
        report "e = " & integer'image(e);
        
        report "f = " & f;
        
        wait;
    end process;
end Behavioral;

In VHDL:

  • Variables are declared using the variable keyword followed by the variable name, its type, and an optional initial value.

  • You can declare multiple variables of the same type in one line.

  • VHDL will not infer the type of variables; you must explicitly declare the type.

  • Variables declared without a corresponding initialization are assigned their default values. For example, the default value for an integer is 0.

  • Unlike Go, VHDL doesn’t have a shorthand syntax for declaring and initializing variables. All variables must be explicitly declared with their types.

  • In VHDL, variables are typically used within processes or subprograms, while signals are used for communication between processes or entities.

To simulate this VHDL code, you would typically use a VHDL simulator like ModelSim or GHDL. The simulation would produce output similar to:

# a = initial
# b = 1, c = 2
# d = true
# e = 0
# f = apple

Note that VHDL is primarily used for hardware description and simulation, so the concept of “running” the code is different from software languages. The code describes a hardware circuit, and a simulator is used to observe its behavior over time.